CENG 5534: Advaced Digital System
M.D. Ciletti, "Advanced Digital Design with the Verilog HDL," 2 edition,
Publisher: Prentice Hall, 2010. ISBN 978-0136019282.
Neil Weste, David Money Harris, "CMOS VLSI Design: A Circuits and Systems Perspective, " 4 Edition, Publisher: Pearson, 2010. ISBN-10: 0321547748. ISBN-13: 978-0321547743. Pong P. Chu, "FPGA Prototyping by Verilog Examples," 3 Version, Publisher: Wiley, 2008. ISBN 978-0-470-18532-2 Verilog HDL: A Guide to Digital Design and Synthesis, 2 Edition. Samir Palnitkar. Publisher: Prentice Hall PTR. Verilog Styles for Synthesis of Digital Systems, David R Smith, Publisher: Prentice Hall, 2000 Many web references and Hands-on training materials. Course slides will be available for download after each class.
VIM Editor ModelSim-Intel FPGA Starter Edition Vivado Webpack/Design Suite Nexys 4 Reference OV7670 Datasheet
Digital electronics/VLSI/Digital System Design
Introduction to industrial IC design flow The latest EDA tools and design methodologies used in industry Combinational and sequential circuit design with Verilog HDL Timing issues in IC design, including setup/hold constrain, the maximum operational frequency, clock tree, and so on Industrial design rules such as clock domain crossing and address alignment Project-based learning (PBL) : a hands-on project including IP design and verification, System-on-Chip (SoC) integration and verification, and FPGA prototype
Know the industrial IC design flow, including algorithm, RTL design, Verification, Synthesis, Layout, and tape-out a chip. Familiar with Verilog HDL, enabling to describe circuit/industrial protocols/algorithms with Verilog. Familiar with the industrial interview questions of an entry-level IC Designer and Verification Engineer, including, but not limited to, timing constrains, clock domain crossing, address alignment of data transfer, and so on. Familiar with IC/FPGA design tools, including Vim editor, ModelSim simulator, and Vivado. Familiar with some industrial specifications including I2C, VGA, and Image Capture. Familiar with FPGA design with a hands-on project -- an image/video processing SoC.
Lec1: Introduction on Integrated Circuit Design Flow (lec1) Lec2: Introduction to Verilog HDL (lec2) Lec3: Matching HDL with Circuit: Basic Combinational and Sequential Circuit Design with Verilog (lec3) Lec4: Timing Constraints – critical/false path, setup & hold time, clock skew, MOF, and so forth (lec4) Lec5: Finite State Machine (FSM) (lec5) Lec6: FSM and Data-Path (FSMD) Design (lec6) Midterm Training #1: VIM, Mentor Graphics ModelSim, and Vivado (tr1) Training #2: Verification (Simulation) Env, Nexys 4 FPGA (tr2) Lec7: Industry specifications: I2C, VGA, and Image Capture (lec7) Project 1: IP design and verification: (Verilog, VIM, and ModelSim), I2C Master, Image Capture Slave, or VGA Master (pr1) Project 2: SoC Integration and Verification (Verilog, VIM, and ModelSim) (pr2) Project 3: Synthesis, Placement & Route, and FPGA Prototype (Verilog, VIM, and Vivado) (pr3) Final Presentation